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CS4218
16-Bit Stereo Audio Codec
Complete CMOS Stereo Audio Input and Output System featuring: General Description
The CS4218 Stereo Audio Codec is a monolithic CMOS device for computer multimedia, automotive, and portable audio applications. It performs A/D and D/A conversion, filtering, and level setting, creating 4 audio inputs and 2 audio outputs for a digital computer system. The digital interfaces of left and right channels are multiplexed into a single serial data bus with word rates up to 50 kHz per channel. ADCs and the DACs use delta-sigma modulation with 64X oversampling. The ADCs and DACs include digital decimation filters and output smoothing filters on-chip which eliminate the need for external anti-aliasing filters. The CS4218 is pin and function compatible with the CS4216 when used in Serial modes 3 and 4. See the Appendix A at the end of this data sheet for details. I2S is a trademark of Philips.
* Delta-Sigma A/D and D/A Converters using 64x Oversampling. * Input Anti-Aliasing and Output Smoothing Filters. * Programmable Input Gain (0 dB to 22.5 dB). * Programmable Output Attenuation (0 dB to 46.5 dB). * Sample frequencies from 4 kHz to 50 kHz. THD < * Low Distortion,for ADC.0.02% for DAC. THD < 0.02% * Low Power Dissipation: 80 mA typical. * Power-Down Mode : 1 mA typical. with CS4216 when used * Pin Compatible and 4 (See Appendix A). in Serial Modes 3 * I2S(TM) Compatible Serial Mode (SM5). or 3.3V Digital Power * Operates from 5V5V Analog Power Supply. Supply. Requires
RESET POWER CONTROL PDN DIGITAL FILTERS D/A
Ordering Information: CS4218-KL 0 to 70C CS4218-KQ 0 to 70C
44-pin PLCC 44-pin TQFP
OUTPUT ATTENUATION
LOUT OUTPUT MUTE ROUT DO1 MF5:DO2/INT MF2:F2/CDIN MF1:F1/CDOUT DI1 MF6:DI2/F1 MF3:DI3/F3/CCLK MF4:MA/CCS REFGND REFBYP REFBUF LIN1 LIN2
SMODE3 SMODE2 SMODE1 SDIN SDOUT SCLK SSYNC
D/A
SERIAL INTERFACE CONTROL
VOLTAGE REFERENCE
DIGITAL FILTERS
MF7:SFS1/F2 MF8:SFS2/F3 FILT CLKIN VD
A/D A/D
INPUT GAIN
INPUT MUX RIN1 RIN2
VA
DGND
AGND
Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
Copyright (c) Crystal Semiconductor Corporation 1996 (All Rights Reserved)
SEP '96 DS135F1 1
CS4218
Contents
Description Cover . . . . . . . . . . . . . . Contents ............. Recommended Operating Conditions . . . . . . Analog Input Characteristics . . . . . . . . Analog Output Characteristics ....... Switching Characteristics . . . . . . . . . Digital Characteristics . . . . . . . . . . A/D Decimation Filter Characteristics . . . . . . D/A Interpolation Characteristics . . . . . . . Absolute Maximum Ratings ........ Filter Response Plots . . . . . . . . . . Typical Connection Diagram . . . . . . . . Overview . . . . . . . . . . . . . Functional Description ......... - Analog Inputs and Outputs . . . . . . . - Offset Calibration ......... - Input Gain and Output Level Setting .... - Muting and the ADC Valid Counter . . . . . - Parallel Digital I/O Pins . . . . . . . . - Reset and Power Down Modes . . . . . . - Audio Serial Interface ........ Serial Interface Modes ......... - Serial Mode 3 .......... - Serial Mode 4 .......... - Serial Mode 5 .......... Power Supply and Grounding . . . . . . . . Pin Diagrams and Descriptions ....... Package Information . . . . . . . . . . Parameter Definitions . . . . . . . . . . Appendix A: CS4218 Compatibility with the CS4216 . . Appendix B: Applications of Serial Mode 4 (SM4) .. Appendix C: Setting CLKIN/SCLK Ratio for Desired Sample .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3 3 4 5 7 8 8 8 9 11 12 12 12 13 13 13 13 13 14 15 15 22 25 26 29 35 36 38 40 43
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CS4218
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, all voltages with respect
to 0V.) Parameter Power Supplies: Digital Digital (Low Voltage) Analog Symbol VD VD VA TA Min 4.75 3.0 4.75 0 Typ 5.0 3.3 5.0 25 Max 5.25 3.6 5.25 70 Units V V V C
Operating Ambient Temperature
ANALOG CHARACTERISTICS( TA = 25C; VA, VD = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD; 1kHz Input Sine Wave; CLKIN = 12.288 MHz; SM3 Slave sub-mode, 256 BPF; 0dB gain/attenuation;Conversion Rate = 48 kHz; SCLK = 12.288 MHz; Measurement Bandwidth is 10 Hz to 20 kHz; Unless otherwise specified.)
Parameter * Symbol Min Typ Max Units Analog Input Characteristics - Minimum gain setting (0 dB); unless otherwise specified. ADC Resolution ADC Differential Nonlinearity Instantaneous Dynamic Range Total Harmonic Distortion Interchannel Isolation Interchannel Gain Mismatch Frequency Response Programmable Input Gain Gain Step Size Absolute Gain Step Error Gain Drift Offset Error Full Scale Input Voltage Input Resistance Input Capacitance (Notes 1,2) (Note 1) (Note 1) 0dB Gain 22.5dB Gain (Note 1) (Note 1) (Note 3) IDR THD 16 80 -0.5 2.5 20 84 80 22.5 1.5 100 - 2.8 0.9 0.02 0.5 +0.2 0.75 50 500 3.1 15 Bits LSB dB % dB dB dB dB dB dB ppm/C LSB LSB Vpp k pF
Notes: 1. This specification is guaranteed by characterization, not production testing. 2. Input resistance is for the input selected. Non-selected inputs have a very high (>1M) input resistance. 3. Operation in Slave sub-modes may yield results lower than the 80 dB minimum. * Parameter definitions are given at the end of this data sheet.
Specifications are subject to change without notice. DS135F1 3
CS4218
ANALOG CHARACTERISTICS
Parameter *
(Continued) Symbol Min Typ Max Units
Analog Output Characteristics - Minimum Attenuation; Unless Otherwise Specified. DAC Resolution DAC Differential Nonlinearity Total Dynamic Range Instantaneous Dynamic Range Total Harmonic Distortion Interchannel Isolation Interchannel Gain Mismatch Frequency Response Programmable Attenuation Attenuation Step Size Absolute Attenuation Step Error Gain Drift REFBUF Output Voltage Offset Voltage Full Scale Output Voltage External Load Impedance Internal Resistor Value for LOUT and ROUT Deviation from Linear Phase Out of Band Energy Power Supply Power Supply Current (Note 8) Operating (VD = 5.0V) Operating (VD = 3.3V) Power Down (1 kHz) 80 65 40 100 85 1 mA mA mA dB (Note 1) (22 kHz to 100 kHz) (Note 1) (Note 5) (Note 5) (Note 5) (Note 1) (Note 6) Maximum output current= 400 A (Note 7) (Note 4) (Note 4) (Note 4) (Note 1) TDR IDR THD 16 80 -0.5 1.9 2.4 10k 400 93 83 80 -46.5 1.5 100 2.1 10 2.7 600 -60 0.9 0.02 0.5 +0.2 0.75 2.3 3.1 800 1 Bits LSB dB dB % dB dB dB dB dB dB ppm/C V mV Vpp Degree dB
Power Supply Rejection
Notes: 4. 10 k, 100 pF load. 5. Tested in SM3, Slave sub-mode, 256 BPF. 6. REFBUF load current must be DC. To drive dynamic loads, REFBUF must be buffered. AC variations in REFBUF current may degrade ADC and DAC performance. 7. No DC load. 8. Typical current: VA = 30mA, VD = 50mA with VD = 5.0V. VA = 30mA, VD = 35mA with VD = 3.3V. Power supply current does not include output loading. * Parameter definitions are given at the end of this data sheet.
4
DS135F1
CS4218
SWITCHING CHARACTERISTICS (TA = 25C; VA, VD = +5V, outputs loaded with 30 pF; Input
Levels: Logic 0 = 0V, Logic 1 = VD) Parameter Input clock (CLKIN) frequency SM3 Multiplier Mode SM3 Master and Slave Modes, SM4, SM5 CLKIN low time CLKIN high time Sample Rate DI pins setup time to SCLK edge DI pins hold time from SCLK edge DO pins delay from SCLK edge SCLK and SSYNC output delay from CLKIN rising SCLK period SCLK high time SCLK low time SDIN, SSYNC setup time to SCLK edge SDIN, SSYNC hold time from SCLK edge SDOUT delay from SCLK edge Output to Hi-Z state Output to non-Hi-Z RESET pulse width low CCS low to CCLK rising CDIN setup to CCLK falling CCLK low to CDIN invalid (hold time) CCLK high time CCLK low time CCLK Period CCLK rising to CDOUT data valid CCLK rising to CDOUT Hi-Z CCLK falling to CCS high RESET low time prior to PDN rising RESET low hold time after PDN rising SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) SM4 (Note 1) tcslcc tdiscc tccdih tcclhh tcclhl tcclkw tccdov tccdot tcccsh trph trhold bit 64 (Note 1) bit 1 (Note 1) All master Modes (Note 1) All master Modes (Notes 1,7) Slave Mode Slave Mode Slave Mode Slave Mode Slave Mode (Note 1) (Note 1) (Note 1) Symbol CLKIN CLKIN tckl tckh Fs ts2 th2 tpd2 tpd3 tsckw tsckh tsckl ts1 th1 tpd1 thz tnz Min 64 1.024 15 15 4 10 8 75 30 30 15 10 15 500 25 15 10 25 25 75 0 100 50 Typ 768 12.288 1/(Fs*bpf) Max 800 12.8 50 30 50 28 12 30 30 Units KHz MHz ns ns kHz ns ns ns ns s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Notes: 7. When the CS4218 is in master modes (SSYNC and SCLK outputs), the SCLK duty cycle is 50%. The equation is based on the selected sample frequency (Fs) and the number of bits per frame (bpf).
DS135F1
5
CS4218
t sckw SCLK [SM3,SM4\ t sckh t sckl t s1 SSYNC [SM3,SM4\ t s1 SDIN [SM3] (SM4) t h1 Bit 1 t pd1 [SM3] SDOUT (SM4) t nz Bit 1 Bit 2 t pd1 Bit 2 Bit 32 (Bit 32) Bit 33 (Bit 1) Bit 63 (Bit 31) Bit 64 (Bit 32) Bit 32 (Bit 32) Bit 33 (Bit 1) Bit 63 (Bit 31) Bit 64 (Bit 32) t hz t h1
Serial Audio Port Timing
MF4:CCS
MF1:CDOUT t cslcc MF3:CCLK t discc MF2:CDIN 0 1 t ccdih MSK 2 DO1 3 LAtt4 4 t cclkw LAtt3 5 LAtt2 6 LAtt1 7 LAtt0 8 RAtt4 9 RAtt3 10 RAtt2 11 t cclkh t cclkl ADV t ccdov LCL
MF4:CCS t cccsh MF1:CDOUT 0 0 1 Err1 Err0
LCL
RCL
DI1
ADV
t ccdot
MF3:CCLK
MF2:CDIN
RGain2 RGain1 RGain0 22 23 24
0 25
0 26
0 27
0 28
0 29
0 30
0 31
0 32
Serial Mode 4. Control Data Serial Port Timing 6 DS135F1
CS4218
SCLK t s2 DIx t pd2 DOx SCLK SSYNC (Master Mode) DI/DO Timing SCLK & SSYNC Output Timing (Master Mode) t h2 CLKIN t pd3 t ckl t ckh
PDN t rph RESET
t rhold
Power Down Mode Timing
DIGITAL CHARACTERISTICS
Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage at I0 = -2.0 mA Low-level Output Voltage at I0 = +2.0 mA Input Leakage Current Output Leakage Current Output Capacitance Input Capacitance
(TA = 25C; VA = 5V, VD = 5V or 3.3V) Symbol VIH VIL VOH VOL (Digital Inputs) Min 2.0 -0.3 VD-0.3 COUT CIN Typ Max VD+0.3 0.8 0.2 10 10 15 15 Units V V V V A A pF pF
(High-Z Digital Outputs) (Note 1) (Note 1)
DS135F1
7
CS4218
A/D Decimation Filter Characteristics
Parameter Passband Frequency Response Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation vs. Frequency (0-0.4Fs) Symbol Min 0 -0.5 0.40Fs 0.60Fs 74 Typ Max 0.40Fs +0.2 0.1 0.60Fs 8/Fs 0.0 Units Hz dB dB Hz Hz dB s s
D/A Interpolation Filter Characteristics
Parameter Passband Frequency Response Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Group Delay Variation vs. Frequency (0-0.4Fs) Symbol Min 0 -0.5 0.40Fs 0.60Fs 74 Typ Max 0.40Fs +0.2 0.1 0.60Fs 8/Fs 0.1/Fs Units Hz dB dB Hz Hz dB s s
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to 0V.)
Parameter Power Supplies: Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Warning: (Power Applied) Digital Analog (Except Supply Pins) Symbol VD VA Min -0.3 -0.3 -0.3 -0.3 -55 -65 Typ Max 6.0 6.0 10.0 VA+0.3 VD+0.3 +125 +150 Units V V mA V V C C
Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
8
DS135F1
CS4218
10 0 -10 -20 -30 -40
0.2 0.1 -0.0 -0.1 Magnitude (dB)
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Magnitude (dB)
-0.2 -0.3 -0.4 -0.5 -0.6 -0.7
-50
-60
-70 -80
-90
-100 Input Frequency (xFs)
-0.8
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 Input Frequency (xFs) 0.50
Figure 1. CS4218 ADC Frequency Response
Figure 2. CS4218 ADC Passband Ripple
0
10
0
-10 -20
-10 Magnitude (dB)
Magnitude (dB)
-30
-40
-50
-20 -30
-40 -50 -60
-60 -70
-80
-70 -80
-90 -100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Input Frequency (xFs)
-90
-100 0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70 Input Frequency (xFs)
Figure 3. CS4218 ADC Transition Band
0.2
Figure 4. CS4218 DAC Frequency Response
0 -10 -20
0.1 -0.0
Magnitude (dB)
Magnitude (dB)
-0.1 -0.2 -0.3
-0.4 -0.5 -0.6
-30 -40 -50 -60 -70 -80
-90
-0.7
-0.8
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (xFs)
-100 0.40 0.43 0.46 0.49 0.52 0.55 0.58 0.61 0.64 0.67 0.70 Input Frequency (xFs)
Figure 5. CS4218 DAC Passband Ripple DS135F1
Figure 6. CS4218 DAC Transition Band 9
CS4218
2.5 2.0
1.5
Phase (degrees)
1.0 0.5 0.0
-0.5 -1.0
-1.5
-2.0 -2.5
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 Input Frequency (xFs)
Figure 7. CS4218 DAC Deviation from Linear Phase
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DS135F1
CS4218
Ferrite Bead +5V Supply + 1 F
0.1 F
2.0 + 1 F 0.1 F 24 VA 15 RIN2 ROUT +
+5V Analog If a separate +5V Analog supply is used, remove the 2.0 ohm resistor > 1.0 F 40 k 0.0022F NPO Right Audio Output
4 VD
Line In 2 Right
26
See Analog Inputs section for suggested input ciruits. LOUT
16
+
> 1.0 F
40 k Line In 2 Left 28
0.0022F NPO
Left Audio Output
LIN2 21 REFBYP 22
0.1 F
+
10 F
CS4218
Line In 1 Right 25 RIN1
REFGND
CLKIN RESET To Optional Input Buffers
0.47F
3 2
20
PDN REFBUF SDOUT SDIN SCLK SSYNC LIN1
13 43 42 44 1 33 37 DI1 DO1
Controller
Line In 1 Left
27
40 Parallel Bits or Sub-Mode Settings or Control Port
MF1:F1/CDOUT SMODE3
SMODE2
39 MF2:F2/CDIN 35 MF3:DI3/F3/CCLK 36 MF4:MA/CCS 38 MF5:DO2/INT 34 MF6:DI2/F1 AGND 23
41 32 29 31
30
SMODE1 MF7:SFS1
MF8:SFS2
Mode Setting
FILT DGND 5
6
C FILT 0.47F Required only for SM3 Multiplier Sub-Mode Refer to the Analog Inputs section for terminating unused line inputs. All other unused inputs should be tied to GND. All NC pins should be left floating.
Note: AGND and DGND pins MUST be on the same ground plane
Figure 8. Typical Connection Diagram
DS135F1
11
CS4218
OVERVIEW The CS4218 contains two analog-to-digital converters, two digital-to-analog converters, adjustable input gain, and adjustable output level control. Since the converters contain all the required filters in digital or sampled analog form, the filters' frequency responses track the sample rate of the CS4218. Only a single-pole RC filter is required for the analog inputs and outputs. Communication with the CS4218 is via a serial port, with separate pins for data input and output. The filters and converters operate over a sample rate range of 4 kHz to 50 kHz.
0.33 uF
Line In Right
5.6K
RIN1 or RIN2
5.6K
300 pF NPO
5.6K Line In Left 5.6K
NPO 300 pF LIN1 or LIN2
0.33 uF
FUNCTIONAL DESCRIPTION Analog Inputs and Outputs Figure 8 illustrates the suggested connection diagram for the CS4218. The line level inputs, LIN1 or LIN2 and RIN1 or RIN2, are selected by an internal input multiplexer. This multiplexer is a source selector and is not designed for realtime switching between inputs at the sample rate. When using the CS4218 as a drop-in replacement for the CS4216, existing recommended circuits (shown in the CS4216 data sheet) may be used as is without any noticeable degradation in performance. Performance may vary with user-specific input circuits and should be checked when contemplating the use of CS4218 in existing CS4216 designs. Unused analog inputs that are not selected have a very high input impedance, so they may be tied to AGND directly. Unused analog inputs that are selected should be tied to AGND through a 0.1 F capacitor. This prevents any DC current flow. The analog inputs are single-ended and internally biased to the REFBUF voltage (nominally
12 Figure 9. Line Inputs.
2.1 V). The REFBUF output should be buffered if it is to be used for microphone phantom power. The use of a single-pole RC filter is recommended for use as an external anti-alias filter for the CS4218. The maximum cutoff frequency (lowpass) should not exceed 200 kHz. A lower value for cuttoff frequency may be used, and is dependent upon the application's input bandwidth. The CS4218 inputs will accept a 1Vrms signal, so a divide by two resistor network will serve as a front-end interface to 2 Vrms line level systems. Figure 9 shows a simple input circuit that includes a gain of 0.5 and the required RC filter. The gain of 0.5 yields a full scale input sensitivity of 2 Vrms with the CS4218 programmable gain set to 0. The analog outputs are also single-ended and centered around the REFBUF voltage. AC coupling capacitors of >1 F are recommended. Refer to Figure 8 for the recommended analog output circuit.
DS135F1
CS4218
When using the CS4218 as a drop-in replacement for the CS4216, the external 600 ohm series resistors on LOUT and ROUT are not required, since they are part of the CS4218 internal circuitry. In applications where both CS4218 and CS4216 are to be used, a board stuff option should be included in the bill of materials which will allow either a 600-ohm or a 0-ohm resistor to be used externally on both LOUT and ROUT. Offset Calibration Both input and output offset voltages are minimized by internal calibration. Offset calibration occurs after exiting a reset or power down condition. During calibration, which takes 194 frames, output data from the ADCs will be all zeros, and will be flagged as invalid. Also, the DAC outputs will be muted. After power down mode or power up, RESET should be held low for a minimum of 50 ms to allow the voltage reference to settle. Changing sample rates in master and slave modes automatically initiates a calibration. Input Gain and Output Level Setting Input gain is adjustable from 0 dB to +22.5 dB in 1.5 dB steps. Output level attenuation is adjustable from 0 dB to -46.5 dB in 1.5 dB steps. Both input and output gain adjustments are internally made on zero-crossings of the analog signal, to minimize "zipper" noise. The gain change automatically takes effect if a zero crossing does not occur within 512 frames.
SSYNC
Muting and the ADC Valid Counter The mute function allows the the user to turn off the output channels ( LOUT and ROUT ). Prior to muting, the attenuation should be gradually ramped to maximum ( 46.5 dB ), taking 1.5dB steps. This significantly reduces any audible artifacts that may be heard once muting is enabled. It is the users responsibility to program the serial host to perform the ramping. The serial data stream contains a "Valid Data" indicator, the ADV bit, for the A/D converters which is low until enough clocks have passed since reset, or low-power (power down mode) operation to have valid A/D data from the filters (i.e., until calibration time plus the full latency of the digital filters has passed.) Parallel Digital Input/Output Pins Parallel digital inputs are general purpose pins whose values are reflected in the serial data output stream to the processor. Parallel digital outputs provide a way to control external devices using bits in the serial data input stream. All parallel digital pins, with the exception of DI1 and DO1, are multifunction and are defined by the serial mode selected. In Serial Mode 3 master modes and Serial Mode 5, two digital inputs and two digital outputs are available. In Serial Mode 3 slave modes, three digital inputs and two digital outputs are available. In Serial Mode 4 only one digital input and digital output exists. Figure 10 shows when the DI pins are latched, and when the DO pins are updated. Reset and Power Down Modes Reset places the CS4218 into a known state and must be held low for at least 50 ms after powerup or a hard power down. In reset, the digital outputs are driven low. Reset sets all control data register bits to zero. Changing sample rates in
SCLK (SM3) DI pins Start of
Frame
DO pins update
latched
Figure 10. Digital Input/Output Timing DS135F1 13
CS4218
master and slave modes automatically initiates a calibration. An RC filter with a time constant greater than 50 ms may be used on the RESET pin. The CS4218 RESET pin has hysterisis to ensure proper resets when using an RC filter. Hard power down mode may be initiated by bringing the PDN pin low. All analog outputs will be driven to the REFBUF voltage which will then decay to zero. All digital outputs will be driven low and then will go to a high impedance state. Minimum power consumption will occur if CLKIN is held low. After leaving the power down state, RESET should be held low for 50 ms to allow the analog voltage reference to settle before calibration is started. Alternatively, soft power down may be initiated in slave modes by reducing the SCLK frequency below the minimum values shown in Table 1. In soft power down the analog outputs are muted and the serial data from the codec will indicate invalid data and the appropriate error code. The parallel bit I/O is still functional in soft power down mode. This is, in effect, a low power mode with only the parallel bit I/O unit functioning.
Audio Serial Interface In Serial Mode 3 (SM3), the audio serial port uses 4 pins: SDOUT, SDIN, SCLK and SSYNC. SDIN carries the D/A converters' input data and control bits. Input data is ignored for frames not allocated to the selected CS4218. SDOUT carries the A/D converters' output data and status bits. SDOUT goes to a high-impedance state during frames not allocated to the selected CS4218. SCLK clocks data in to and out of the CS4218. SSYNC indicates the start of a frame and/or sub-frame. SCLK and SSYNC must be synchronous to the master clock. Serial Mode 4 (SM4) is similar to SM3 with the exception of the control information. In Serial Mode 4, the control information is entered through a separate asynchronous control port. Therefore, the audio serial port only contains audio data, which reduces the number of bits on the audio port from 64 to 32 per codec. This is useful for lower bit rate serial hosts. Serial Mode 5 (SM5) is compatible with the I2STM serial data protocol. SM5 is a Master mode only. As in SM3, 4 pins are used: SDOUT, SDIN, SCLK, and SSYNC. The serial port protocol is based on frames consisting of 1, 2, or 4 sub-frames. The frame rate is the system sample rate. Each sub-frame is used by one CS4218 device. Up to 4 CS4218s may be attached to the same serial control lines. SFS1 and SFS2 are tied low or high to indicate to each CS4218 which sub-frame is allocated for it to use. Serial Data Format In SM3 and SM5, a sub-frame is 64 bits in length and consists of two 16-bit audio values and two 16-bit control fields. In SM4 a subframe is 32 bits in length and only contains the two 16-bit audio fields; the control data is loaded through a separate port. The audio data is MSB
DS135F1
Bits Per Frame
Minimum SCLK Frequency CLKIN CLKIN CLKIN CLKIN / / / / 96 48 24 12
For All Modes Except SM3 Multiplier Sub Mode
32 64 128 256
SM3 Multiplier Sub Mode
64 128 256 (16 * CLKIN) / 48 (16 * CLKIN) / 24 (16 * CLKIN) / 12
Table 1. Soft Power Down Conditions (Slave Modes only)
14
CS4218
first, 2's complement format. Sub-frame bit assignments are shown in Figure 13. Control data bits all reset to zero.
the master CLKIN is multiplied internally by 16, so a 16xFs input clock must be provided.
SERIAL MODE 3, (SM3) CS4218 SERIAL INTERFACE MODES The CS4218 has three serial port modes, selected by the SMODE1, SMODE2 and SMODE3 pins. In all modes, CLKIN, SCLK and SSYNC must be derived from the same clock source. SM3 was designed as an easy interface to general purpose DSPs and provides features such as master and slave sub-modes and variable frame sizes. SM4 is similar to SM3 but splits the audio data from the control data thereby reducing the audio serial bus bandwidth by half. The control data is transmitted through a control serial port in SM4. SM5 is compatible with the I2S serial data protocol. Table 2 lists the three serial port modes available, along with some of the differences between modes. The first three columns in Table 2 select the serial mode. The "SCLK Bit Center" column indicates whether SCLK is rising or falling in the center of a bit period. The "Sub-frame Width" column indicates how many bits are in an individual codec's sub-frame. In SM3 and SM4, the number of bits per frame is programmable. In all modes, SCLK and SSYNC must be synchronous to the master clock. The last column in Table 2 lists the master frequencies used by the codec. In the SM3 Multiplier sub-modes,
SMODE PINS 3 2 1 0 0 0 0 1
Serial Mode 3, Master and Slave sub-modes are enabled by setting SMODE3 = 0, SMODE2 = 1 and SMODE1 = 0. SM3 Multiplier Sub-Modes are enabled by setting SMODE 3 = 0, SMODE 2 = 0, and SMODE 1 = 0. Serial Mode 3 is designed to interface easily to DSPs. Figure 11 illustrates the serial data in, SDIN, sub-frame for all SM3 sub-modes. Figure 12 also illustrates the serial data out, SDOUT, subframe for all SM3 sub-modes. Figure 13 shows sub-frame bit definitions. In SM3 master sub-modes, MF5:DO2 is a general purpose output and MF6:DI2 is a general purpose input. The other six multifunction pins are used to select sub-modes under SM3. In SM3 slave sub-modes, MF3:F3 is configured as an additional general purpose input. SM3 is divided into four sub-modes, Master (SM3-M), Slave (SM3-S), Multiplier Master (SM3-MM), and Multiplier Slave (SM3-MS). SM3-M and SM3-S are identical to the CS4216 SM3 Master and Slave sub-modes, respectively. In SM3-M and SM3-MM sub-modes, the CS4218 generates SSYNC and SCLK, while in SM3-S and SM3-MS sub-modes SSYNC and
SCLK & SSYNC Master Frequency CLKIN = 16xFs CLKIN = 256xFs CLKIN or SCLK = 256xFs CLKIN = 256xFs
Serial Mode SM3* SM5 SM3 SM4
SCLK Bit Center Falling Rising
Sub-frame Width 64 bits 64 bits
Bits per Frame (BPF)
0 0 1 1 x
0 1 0 1 x
64/128/256 Master/Slave 64 Master 64/128/256 Master/Slave 32/64/128 Master/Slave
Falling 64 bits Factory Test mode Falling 32 bits
Contains audio data only. Control information is entered through a separate serial port. * SM3 Multiplier sub-modes. Table 2. Serial Port Modes DS135F1 15
CS4218
SCLK must be generated externally. When the codec is the serial port master, the serial port signal transitions are controlled with respect to the internal analog sampling clock to minimize the amount of digital noise coupled into the analog section. Since SSYNC and SCLK are externally derived when the codec slaves to the serial port, optimum noise management cannot be obtained; therefore, master modes should be used whenever possible. Multiplier sub-modes are identical to the SM3 modes except the master clock, CLKIN, is internally multiplied by 16. A 0.47 F capacitor must be tied to the FILT pin when using the Multiplier sub-modes.
Master Clock Frequency In SM3-M and SM3-S sub-modes, the master clock, CLKIN, must be 256 x Fsmax. For example, given a 48 kHz maximum sample frequency, the master clock frequency mu st be 12.288 MHz. In SM3-MM and SM3-MS submodes, CLKIN must be 16xFsmax. For example, given a 48 kHz maximum sample frequency, the master clock frequency must be 768 kHz. SCLK and SSYNC must be synchronous to the master clock.
Sub-frame Sub-frame
Word A Word B
MUTE
MSB
ISL ISR LG3 LG2 LG1 LG0 RG3 RG2 RG1 RG0 MSB
DAC - Left Word
00000
DAC - Right Word
LA4 LA3 LA2 LA1 LA0 RA4 RA3 RA2 RA1 RA0 DO1 DO2
LSB
LSB
VER3 VER2 VER1 VER0
MSB
MSB
ADV LCL RCL ER3 ER2 ER1 ER0
LSB
LSB
ADC - Left Word
00000
ADC - Right Word
D I1 D I2 D I3
16
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
00
00
Figure 11. Serial Data Input Format - SM3, SM5. Sub-frame Sub-frame
Word A
Word B
000000010000
X
Figure 12. Serial Data Output Format - SM3, SM5. DS135F1
CS4218
SM3 and SM5 Subframe Bit Definitions for SDIN Bit(s) Symbol Description 1-16 DAC-LEFT Audio Data, DAC Left 2's Complement data, MSB first (Bit 1 = MSB) 17-21 unused Unused, write with 0's 22 MUTE Mute DAC Outputs 0 = Outputs ON 1 = Outputs MUTED 23 ISL Input Mux, Left Select 0 = LIN1 1 = LIN2
Bit(s) 33-48
Symbol DAC-RIGHT
49,50 51 - 55
unused LA4 - LA0
56 - 60
RA4 - RA0
Input Mux, Right Select 0 = RIN1 1 = RIN2 25-28 LG3 - LG0 Left Input Gain 1.5dB Increments. 0000 = No gain (0dB) 1111 = 22.5 dB gain 29-32 RG3 - RG0 Right Input Gain 1.5dB Increments. 0000 = No gain (0dB) 1111 = 22.5 dB gain SM3 and SM5 Subframe Bit Definitions for SDOUT Bit(s) Symbol Description 1-16 ADC-LEFT Audio Data, ADC Left 2's Complement data, MSB first (Bit 1 = MSB) 17-21 reserved These bits can be 0 or 1
24
ISR
61
DO1
62
DO2
Description Audio Data, DAC Right 2's Complement data, MSB first (Bit 33 = MSB) Unused, write with 0's Left Output Attenuation 1.5dB Increments. 00000 = no atten. (0dB) 11111 = 46.5dB atten. Right Output Attenuation 1.5dB Increments. 00000 = no atten. (0dB) 11111 = 46.5dB atten. Digital Output 1 0 = Output LOW 1 = Output HIGH Digital Output 2 0 = Output LOW 1 = Output HIGH Unused, write with 0's
63,64
unused
Bit(s) 29-32
Symbol VER3-VER0
33-48
ADC-RIGHT
22
ADV
23
LCL
24
RCL
25-28
ER3 - ER0
ADC Valid Data 0 = Invalid ADC data 1 = Valid ADC data ADC Left Clipping 0 = Normal 1 = Clipping ADC Right Clipping 0 = Normal 1 = Clipping Error Word 0000 = Normal, no error 0001 = Input Sub-Frame Bit 21 Set. Control data is ignored. 0010 = Sync Pulse Error Outputs muted. 0011 = Soft PowerDown Outputs muted.
49-60
reserved
Description CS4218 Version Number 0000 = Rev A 1000 = Rev B and later Audio Data, ADC Right 2's Complement data, MSB first (Bit 33 = MSB) These bits can be 0 or 1
61
DI1
62
DI2
63*
DI3
Digital Input 1 0 = Input LOW 1 = Input HIGH Digital Input 2 0 = Input LOW 1 = Input HIGH Digital Input 3 0 = Input LOW 1 = Input HIGH * SM3-S sub-modes only
64
unused
don't care
Figure 13. SM3 / SM5 Subframe, Bit definitions DS135F1 17
CS4218
Master Sub-Mode (SM3-M) Master su b-mod e is selected by setting MF4:MA = 1, which configures SSYNC and SCLK as outputs from the CS4218. During power down, SSYNC and SCLK are driven high impedance, and during reset they both are driven low. In Master sub-mode the number of bits per frame determines how many codecs can occupy the serial bus and is illustrated in Figure 14. Bits Per Frame (Master Sub-Modes) MF8:SFS2 selects the number of bits per frame. The two options are MF8:SFS2 = 1 which selects 128 bits per frame, and MF8:SFS2 = 0 which selects 64 bits per frame. Selecting 128 bits per frame (MF8:SFS2 = 1) allows two CS4218s to operate from the same serial bus since each codec requires 64 bit periods. The sub-frame used by an individual codec is selected using MF7:SFS1. MF7:SFS1 = 0 selects sub-frame 1 which is the first 64 bits following the SSYNC pulse. MF7:SFS1 = 1 selects sub-frame 2 which is the last 64 bits of the frame. Selecting 64 bits per frame (MF8:SFS2 = 0) allows only one CS4218 to occupy the serial port. Since there is only one sub-frame (which is equal to one frame), MF7:SFS1 is defined differently in this mode. MF7:SFS1 selects the format of SSYNC. MF7:SFS1 = 0 selects an SSYNC pulse one SCLK period high, directly preceding the data as shown in the center portion of Figure 14. This format is used for all other master and slave sub-modes in SM3. If MF7:SFS1 = 1, an alternate SSYNC format is chosen in which SSYNC is high during the entire Word A (32 bits), which includes the left sample, and low for the entire Word B (32 bits), which includes the right sample. This alternate format for SSYNC is illustrated in the bottom portion of Figure 14 and is only available in SM3-M and SM3-MM sub-modes with 64 bits per frame. A
18
more detailed timing diagram for the 64 bits-perframe master sub-modes is shown in Figure 15. Sample Frequency Selection (Master Sub-Modes) In SM3-M and SM3-MM sub-modes, the multifunction pins MF1:F1, MF2:F2, and MF3:F3 are used to select the sample frequency divider. Table 3 lists the decoding for the sample frequency select pins where the sample frequency selected is CLKIN/N. Also shown are the sample frequencies obtained by using one of two example master clocks: either 12.288 MHz or 11.2896 MHz. Changing sample frequency automatically initiates a calibration cycle.
MF1: F1 0 0 0 0 1 1 1 1
MF2: F2 0 0 1 1 0 0 1 1
MF3: F3 0 1 0 1 0 1 0 1
N
Fs (kHz) with CLKIN or 16xCLKIN 12.288 11.2896 MHz MHz 48.00 32.00 24.00 19.20 16.00 12.00 9.60 8.00 44.10 29.40 22.05 17.64 14.70 11.025 8.82 7.35
256 384 512 640 768 1024 1280 1536
Table 3. SM3-M/SM3-MM/SM5, Fs Select
DS135F1
CS4218
FRAME n 128 SCLK Periods Sub-frame 1 DATA SSYNC Word A Word B Sub-frame 2 Word A Word B
FRAME (n+2)
FRAME (n+3)
Sub-frame 1 Word A Word B
Sub-frame 2 Word A Word B
Sub-frame 1 Word A Word B
MF8: MF7: SubSFS2 SFS1 frame 1 1 0 1 1 2
FRAME n 64 SCLK Periods Sub-frame 1 DATA SSYNC FRAME n 64 SCLK Periods Sub-frame 1 DATA SSYNC Word A Word B Word A Word B
FRAME (n+1) Sub-frame 1 Word A Word B
FRAME (n+2) Sub-frame 1 Word A Word B
FRAME (n+3) Sub-frame 1 Word A Word B
FRAME (n+4) Sub-frame 1 Word A Word B MF8: MF7: SubSFS2 SFS1 frame 0 0 1
FRAME (n+1) Sub-frame 1 Word A Word B
FRAME (n+2) Sub-frame 1 Word A Word B
FRAME (n+3) Sub-frame 1 Word A Word B
FRAME (n+4) Sub-frame 1 Word A Word B MF8: MF7: SubSFS2 SFS1 frame 0 1 1
Figure 14. SM3-M and SM3-MM Sub-Modes.
SCLK
SDIN SDOUT
MSB Word A 32 CLOCKS
LSB
MSB Word B 32 CLOCKS
LSB
SSYNC (MF7:SFS1=0)
SSYNC (MF7:SFS1=1)
Figure 15. Detailed SM3-M and SM3-MM Sub-Modes, 64 BPF.
DS135F1
19
CS4218
Slave Sub-Mode (SM3-S) In SM3, Slave sub-mode is selected by setting MF4:MA = 0 which configures SSYNC and SCLK as inputs to the CS4218. These two signals must be externally derived from CLKIN. In SM3-S and SM3-MS sub-modes, the phase relationship between SCLK/SSYNC and CLKIN cannot be controlled since SCLK and SSYNC are externally derived. Therefore, the noise performance may be slightly worse than when using the master sub-modes. The number of sub-frames on the serial port is selected using MF1:F1 and MF2:F2. In SM3-S and SM3-MS sub-modes, MF3:F3 works as an additional general purpose input DI3. Figures 16 through 18 illustrate the SM3-S and SM3-MS sub-mode formats. Bits per Frame (Slave Sub-Modes) In slave sub-modes, MF1:F1 and MF2:F2 select the number of bits per frame, which determines how many CS4218s can occupy one serial port. Table 4 lists the decoding for MF1:F1 and MF2:F2. When set for 64 SCLKs per frame, one device occupies the entire frame; therefore, a sub-frame is equivalent to a frame. MF7:SFS1 and MF8:SFS2 must be set to zero. When set for 128 SCLKs per frame, two devices can occupy the serial port, with MF7:SFS1 seMF1: F1 0 0 1 1 MF2: F2 0 1 0 1 Bits per Frame 64 128 256 256 Sample Frequency/ SCLK ratio to CLKIN sensed ratio to CLKIN sensed ratio to CLKIN sensed fixed. = 256xFs
lecting the particular sub-frame. MF8:SFS2 must be set to zero. See Figure 17. When set for 256 SCLKs per frame (MF1:F1, MF2:F2 = 10), four devices can occupy the serial port. In this format both MF8:SFS2 and MF7:SFS1 are used to select the particular subframe. In all three of the above slave sub-mode formats, the frequency of the incoming SCLK signal, in relation to the master clock provided on the CLKIN pin, determines the sample frequency. The CS4218 determines the ratio of SCLK to CLKIN and sets the internal operating frequency accordingly. Table 5 lists the SCLK to CLKIN frequency ratio used to determine the codec's sample frequency. To obtain a given sample frequency, SCLK must equal CLKIN divided by the number in the table, based on the number of bits per frame. As an example for SM3-S, assuming 64 BPF (bits per frame) and CLKIN = 12.288 MHz, if a sample frequency of 24 kHz is desired, SCLK must equal CLKIN divided by 8 or 1.536 MHz. A change in sample rate automatically initiates a calibration cycle. When MF1:F1 = MF2:F2 = 1, SCLK is used as the master clock and is assumed to be 256 times the sample frequency. In this mode, CLKIN is
SCLK to CLKIN Ratio Fs (kHz) Fs (kHz) BPF BPF BPF with CLKIN with CLKIN or 16xCLKIN or 16xCLKIN 256 128 64 12.288 MHz 11.2896 MHz 1 1.5 2 2.5 3 4 5 6 2 3 4 5 6 8 10 12 4 6 8 10 12 16 20 24 48.00 32.00 24.00 19.20 16.00 12.00 9.60 8.00 44.10 29.40 22.05 17.64 14.70 11.025 8.82 7.35
SCLK is master clock. CLKIN is not used. Not available in Multiplier Slave sub-mode.
Table 4. SM3-S/SM3-MS, Bits per Frame. 20
Table 5. SM3-S/SM3-MS, Fs Select. DS135F1
CS4218
ignored and the sample frequency is linearly scaled with SCLK. (The CLKIN pin must be tied low.) This mode also fixes SCLK at 256 bits per frame with MF7:SFS1 and MF8:SFS2 selecting the particular sub-frame. This master clocking option is not available in the multiplier (SM3-MS) sub-mode.
* * *
Set SMODE1 = SMODE2 = SMODE3 = 0. This selects SM3 Multiplier mode. CLKIN must be 16*Fs, as opposed to 256*Fs used for SM3-M and SM3-S. A 0.47uF capacitor must be connected to the FILT pin as shown in Figure 8.
Multiplier Sub-Modes (SM3-MM and SM3-MS) The SM3 Multiplier sub-modes are identical to the SM3-M and SM3-S sub-modes with the following exceptions:
Master / Slave setup, frame formats, and sample rate selection are identical to SM3-M and SM3S. Please note that the MF1:F1 = MF2:F2 = 1 slave configuration supported by the SM3-S submode it not available in SM3-MS sub-mode.
FRAME n 64 SCLK Periods Sub-frame 1 DATA SSYNC Word A Word B
FRAME (n+1)
FRAME (n+2)
FRAME (n+3)
Sub-frame 1 Word A Word B
Sub-frame 1 Word A Word B
Sub-frame 1 Word A Word B MF8: MF7: SubSFS2 SFS1 frame 0 0 1
Figure 16. SM3-S and SM3-MS - 64 BPF; MF1:F1, MF2:F2 = 00
FRAME n 128 SCLK Periods Sub-frame 1 DATA Word A Word B Sub-frame 2 Word A Word B FRAME (n+1) FRAME (n+2)
Sub-frame 1 Word A Word B
Sub-frame 2 Word A Word B
Sub-frame 1 Word A Word B
MF8: MF7: SubSFS2 SFS1 frame 0 0 0 1 1 2
SSYNC
Figure 17. SM3-S and SM3-MS - 128 BPF; MF1:F1, MF2:F2 = 01
FRAME n 256 SCLK Periods Sub-frame 1 DATA Word A Word B Sub-frame 2 Word A Word B Sub-frame 3 Word A Word B Sub-frame 4 Word A Word B FRAME (n+1) MF8: MF7: SubSFS2 SFS1 frame Sub-frame 1 Word A Word B 0 0 1 1 0 1 0 1 1 2 3 4
SSYNC
Figure 18. SM3-S and SM3-MS - 256 BPF; MF1:F1, MF2:F2 = 10 DS135F1 21
CS4218
SERIAL MODE 4, (SM4) Serial Mo de 4 is en ab led by setting SMODE3 = 1. Both Master and Slave submodes are available and are selected by setting the SMODE2 and SMODE1 pins as shown in Table 6. In Master sub-mode, the phase relationship between SCLK/SSYNC and CLKIN is controlled to minimize digital noise coupling into the analog section. Therefore, Master submo de may yield slightly better noise performance than Slave sub-mode. In Slave sub-mode, SCLK and SSYNC must be synchronous to CLKIN. In serial mode 4, the CLKIN frequency must be 256 times the highest sample frequency needed. SM4 differs from SM3 and SM5 in that SM4 splits the audio data from the control data, with the control data on an independent serial port. This reduces the audio serial bus bandwidth by half, providing an easier interface to low-cost DSPs. The audio serial port sub-frame is illustrated in Figure 19 for SM4.
SMODE1 0 0 1 1 SMODE2 0 1 0 1 SM4, Sub-Mode Master, 32 BPF Slave, 128/64/32 BPF Master, 64 BPF, TS1 Master, 64 BPF, TS2
Master Sub-Mode (SM4) Master sub-mode configures SSYNC and SCLK as outputs from the CS4218. During power down, SSYNC and SCLK are driven high impedance, and during reset they both are driven low. There are two SM4 Master sub-modes. One allows 32 bits per frame and the other allows 64 bits per frame. As shown in Table 6, the SMODE1 and SMODE2 pins select the particular Master sub-mode (as well as the Slave sub-mode). When SMODE1 is set to zero, SMODE2 selects either Master sub-mode with 32-bit frames, or Slave sub-mode. SMODE1,SMODE2 = 00 selects Master submode where a frame = sub-frame = 32 bits. This sub-mode allows only one codec on the audio serial bus, with the first 16 bits being the left channel and the second 16 bits being the right channel. The Appendix B section contains more information on low-cost implementations of this sub-mode. SMODE1 = 1 selects Master sub-mode with a frame width of 64 bits. This sub-mode allows up to two codecs to occupy the same bus. SMODE2 is now used to select the particular time slot. If SMODE2 = 0 the codec selects time slot 1, which is the first 32 bits. If SMODE2 = 1 the codec selects time slot 2, which is the second 32 bits.
Sub-Frame
Table 6. SM4 Sub-Modes.
(master) SSYNC (slave) SCLK
23
32 1
16 17
32 1
MSB
MSB
24 25
SDOUT
ADC - Right Word
ADC - Left Word
ADC - Right Word
MSB
LSB
LSB
LSB
ADC - Left Word
MSB
MSB
SDIN
DAC - Right Word
DAC - Left Word
DAC - Right Word
MSB
LSB
LSB
LSB
DAC - Left Word
Figure 19. SM4-Audio Serial Port, 32 BPF 22 DS135F1
14
8 9
CS4218
In Master sub-mode, multifunction pins MF6:F1, MF7:F2, and MF8:F3 select the sample frequency as shown in Table 7. This table indicates how to obtain standard audio sample frequencies given on e of two CLKIN freq uencies: 12.288 MHz or 11.2896 MHz. Other CLKIN frequencies may be used with the corresponding sample frequencies being CLKIN/N. A change in sample rate automatically initiates a calibration cycle.
MF6: F1 0 0 0 0 1 1 1 1 MF7: F2 0 0 1 1 0 0 1 1 MF8: F3 0 1 0 1 0 1 0 1 N Fs (kHz) with CLKIN 12.288 11.2896 MHz MHz 48.00 32.00 24.00 19.20 16.00 12.00 9.60 8.00 44.10 29.40 22.05 17.64 14.70 11.025 8.82 7.35
256 384 512 640 768 1024 1280 1536
SM4-Slave allows up to four codecs to occupy the same audio serial port. Table 8 lists the pin configurations required to set the serial audio port up for 32, 64, or 128 bits-per-frame (BPF). Since each codec requires one sub-frame of 32 bits, 64 bits-per-frame allows up to two codecs to occupy the same audio serial port, and 128 bits-per-frame allows up to four codecs to occupy the same audio serial port. When set up for more than one codec on the bus, other pins are needed to select the particular time slot (TS) associated with each codec. MF8:SFS2 selects the time slot when in 64 BPF mode, and MF8:SFS2 and MF7:SFS1 select one of four time slots when in 128 bits-per-frame mode. Table 8 lists the decoding for time slot selection.
MF6: F1 0 0 0 0 1 1 1 1 MF7: SFS1 0 0 1 1 0 1 0 1 MF8: SFS2 0 1 0 1 0 0 1 1 Bits Per Frame (BPF) 32 Reserved 64 64 128 128 128 128 1 2 1 2 3 4 Time Slot (TS) 1
Table 7. SM4-Master, Fs Select
Slave Sub-Mode (SM4) In SM4, Slave sub-mode is selected by setting SMODE1,SMODE2 = 01. This mode configures SSYNC and SCLK as inputs to the CS4218. These two signals must be externally derived from CLKIN. Since the CS4218 has no control over the phase relationship of SSYNC and SCLK to CLKIN, the noise performance in Slave sub-mode may be slightly worse than when using Master sub-mode. The CS4218 internally sets the sample frequency by sensing the ratio of SCLK to CLKIN; therefore, for a given CLKIN frequency, the sample frequency is selected by changing the SCLK frequency. A change in sample rate automatically initiates a calibration cycle. Table 9 shows the sample rates generated with two example clocks.
Table 8. SM4-Slave, Audio Port BPF & TS Select
SCLK to CLKIN Ratio Fs (kHz) Fs (kHz) BPF BPF BPF with CLKIN with CLKIN 128 64 32 12.288 MHz 11.2896 MHz 2 3 4 5 6 8 10 12 4 6 8 10 12 16 20 24 8 12 16 20 24 32 40 48 48.00 32.00 24.00 19.20 16.00 12.00 9.60 8.00 44.10 29.40 22.05 17.64 14.70 11.025 8.82 7.35
Table 9. SM4-Slave, Fs Select.
DS135F1
23
CS4218
Serial Control Port (SM4) Serial Mode 4 separates the audio data from the control data. Since control data such as gain and attenuation do not change often, this mode reduces the bandwidth needed to support the audio serial port. The control information is entered through a separate port that can be asynchronous to the audio port and only needs to be updated when changes in the control data are needed. After a reset or power down, the control port must be written once to initialize it if the port will be accessed to read or write control bits. This initial write is considered a "dummy" write since the data is ignored by the codec. A second write is needed to configure the codec as desired. Then, the control port only needs to be written to when a change is desired, or to obtain the status information. The control port does not function if the master clock is not operating. When the control port is used asynchronously to the audio port, the noise performance may be slightly degraded due to the asynchronous digital noise. Since control data does not need to be accessed each audio frame, an interrupt pin, MF5:INT, is included in this mode and will go low when status has changed. The control port serial data
format is illustrated in Figure 20. The control port uses one of the multifunction pins as a chip select line, MF4:CCS, that must be low for entering control data. Although only 23 bits contain useful data on MF2:CDIN, a minimum of 31 bits must be written. If more than 31 bits are written without toggling MF4:CCS, only the first 31 are recognized. MF1:CDOUT contains status information that is output on the rising edge of MF3:CCLK. Status information is repeated at the end of the frame, bits 25 through 30, to allow a simple 8-bit shift and latch register to store the most important status information using the rising edge of MF4:CCS at the latch control (see Appendix B). Interrupt Pin - MF5:INT Serial Mode 4 defines the multifunction pin MF5:INT as an open-collector interrupt pin. In SM4, this pin requires a pullup resistor and will go low when the ADV bit or DI1 pin change, or a rising edge on the LCL or RCL bits occurs, or by exiting an SCLK out of range condition (Error = 3). The interrupt may be masked by setting the MASK bit in the control serial data port. MF5:INT is reset by reading the control serial port.
MF4:CCS
MF3:CCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 MASK DO1
MF2:CDIN
4
0
0 4 Right 0 Left D/A Att. D/A Att.
MUTE ISL ISR
3 Left 0 3 Right 0 A/D Gain A/D Gain 0 0 0 0 0 0 0 0
MF1:CDOUT
0
103 0 10 Err Version 0 0 0 1 Err
ADV LCL RCL DI1
Figure 20. SM4 - Control Serial Port 24 DS135F1
LCL RCL DI1 ADV
CS4218
SERIAL MODE 5 (SM5) The Serial Mode 5 is compatible with the Phillips I2S serial protocol. SM5 is enabled by setting SMODE3 = 0, SMODE2 = 0, and SMODE1 = 1. This is a master mode fixed at 64 BPF. Figure 21 shows the frame format of the SM5. Figure 22 shows the detailed frame format. The multi-function pins MF4, MF7, and MF8 are not used in this mode. MF4 should be tied to VD, and MF7 and MF8 should be tied to ground. Figures 11 & 12 illustrate the serial data in, SDIN, and serial data out, SDOUT, sub-frames for SM5.
Sample Frequency Selection The multifunction pins MF1:F1, MF2:F2, and MF3:F3 are used to select the sample frequency divider. Table 3 lists the decoding for the sample frequency select pins where the sample frequency selected is CLKIN/N. Also shown are the sample frequencies obtained by using one of two example master clocks. A change in sample rate will automatically initiate a calibration cycle.
FRAME n 64 SCLK Periods
FRAME (n+1)
FRAME (n+2)
FRAME (n+3)
FRAME (n+4)
DATA SSYNC
Word A
Word B
Word A
Word B
Word A
Word B
Word A
Word B
Word A
Word B
1 SCLK
Figure 21. Serial Mode 5
FRAME SCLK
SDIN SDOUT
LSB
MSB
LSB
MSB
LSB
Word A 32 CLOCKS SSYNC
Word B 32 CLOCKS
Figure 22. Detailed Serial Mode 5. DS135F1 25
CS4218
Power Supply and Grounding The CS4218, along with associated analog circuitry, should be positioned in an isolated section of the circuit board, and have its own, separate, ground plane. On the CS4218, the analog and digital grounds are internally connected; therefore, the AGND and DGND pins must be externally connected with no impedance between them. The best solution is to place the entire chip on a solid ground plane as shown in Figure 23. Preferably, it should also have its own power plane. The +5V (or +3.3V) supply must be connected to the CS4218 via a ferrite bead, positioned closer than 1" to the device. If using +5V for VD, the VA supply can be derived from VD, as shown in Figure 8. Alternatively, a separate +5V analog supply may be used for VA, in which case, the 2.0 resistor between VA and VD should be removed. A single connection between the CS4218 ground (analog ground) and the board digital ground should be positioned as shown in Figure 23. Figure 24 illustrates the optimum ground and decoupling layout for the CS4218 assuming a surface-mount socket and leaded decoupling capacitors. Surface-mount sockets are useful since the pad locations are identical to the chip pads; therefore, assuming space for the socket is left on the board, the socket can be optional for production. Figure 24 depicts the top layer, containing signal traces, and assumes the bottom or inter-layer contains a fairly solid ground plane. The important points are that there is solid ground plane under the codec on the same layer as the codec and it connects all ground pins with thick traces providing the absolute lowest impedance between ground pins. The decoupling capacitors are placed as close as possible to the device which, in this case, is the socket boundary. The lowest value capacitor is placed closest to the codec. Vias are placed near the AGND and DGND pins, under the IC, and should attach
to the solid ground plane on another layer. The negative side of the decoupling capacitors should also attach to the same solid ground plane. Traces and vias bringing power to the codec should be large, which minimizes the impedance. Although not shown in the figures, the trace layers (top layer in the figures) should have ground plane fill in-between the traces to minimize coupling into the analog section. If using all surface-mount components, the decoupling capacitors should be placed on the same layer as the codec and in the positions shown in Figure 25. The vias shown are assumed to attach to the appropriate power and ground layers. Traces and vias bringing power to the codec should be as large as possible to minimize the impedance. If using a through-hole socket, effort should be made to find a socket with minimum height, which will minimize the socket impedance. When using a through hole socket, the vias under the codec in Figure 24 and 25 are not needed since the pins serve the same function.
26
DS135F1
CS4218
>1/8"
Digital Ground Plane
Ground Connection
Analog Ground Plane
CS4218
Note that the CS4218 is oriented with its digital pins towards the digital end of the board.
Power Connection use Ferrite Bead
CPU & Digital Logic
Codec digital signals
Codec analog signals & Components
Figure 23. CS4218 Board Layout Guideline
0.1 uF
1.0 uF
+
Analog Supply
1 1.0 uF 0.1 uF
+ 10 uF
Digital Supply
+
Figure 24. CS4218 Decoupling Layout Guideline
DS135F1
0.1 uF
27
CS4218
0.1 uF
+ 1.0 uF
Analog Supply
1 Digital Supply +
0.1 uF
0.1 uF 1.0 uF +
10 uF
Figure 25. CS4218 Surface Mount Decoupling Layout
28
DS135F1
CS4218
PIN DESCRIPTIONS
SSYNC RESET CLKIN VD DGND FILT NC NC NC NC NC NC PDN NC ROUT LOUT NC NC NC REFBUF REFBYP REFGND
44 1 2 3 4 5 6 7 8 9 10 11 12
42
40
38
36
34 33 32 31 30 29 28 27 26 25 24 23
CS4218 44-PIN TQFP (Q) Top View
14 16 18 20 22
SCLK SDOUT SDIN SMODE3 MF1:F1/CDOUT MF2:F2/CDIN MF5:DO2/INT DO1 MF4:MA/CCS MF3:DI3/F3/CCLK MF6:DI2/F1 DI1 SMODE2 MF7:SFS1/F2 MF8:SFS2/F3 SMODE1 LIN2 LIN1 RIN2 RIN1 VA AGND MF6 DI2 DI2 DI2 F1 F1 MF7 MF8 Tie to DGND Tie to DGND SFS1 SFS1 SFS1 F2 SFS2 SFS2 SFS2 F3
SM SM5 3-SL 3-MA 4-SL 4-MA
MF1 F1 F1 F1 CDOUT CDOUT
MF2 F2 F2 F2 CDIN CDIN
MF3 F3 DI3 F3 CCLK CCLK
MF4 Tie to VD MA MA CCS CCS
MF5 DO2 DO2 DO2 INT INT
DS135F1
29
CS4218
SSYNC RESET CLKIN VD DGND FILT NC NC NC NC NC NC PDN NC ROUT LOUT NC NC NC REFBUF REFBYP REFGND
7 8 9 10 11 12 13 14 15 16 17
6
4
2 1 44
42
40
CS4218 CS4216 44-PIN PLCC (L) Top View
18 20 22 24 26 28
39 38 37 36 35 34 33 32 31 30 29
SCLK SDOUT SDIN SMODE3 MF1:F1/CDOUT MF2:F2/CDIN MF5:DO2/INT DO1 MF4:MA/CCS MF3:DI3/F3/CCLK MF6:DI2/F1 DI1 SMODE2 MF7:SFS1/F2 MF8:SFS2/F3 SMODE1 LIN2 LIN1 RIN2 RIN1 VA AGND MF6 DI2 DI2 DI2 F1 F1 MF7 tie to DGND SFS1 SFS1 SFS1 F2 MF8 tie to DGND SFS2 SFS2 SFS2 F3
SM SM5 3-SL 3-MA 4-SL 4-MA
MF1 F1 F1 F1 CDOUT CDOUT
MF2 F2 F2 F2 CDIN CDIN
MF3 F3 DI3 F3 CCLK CCLK
MF4 tie to VD MA MA CCS CCS
MF5 DO2 DO2 DO2 INT INT
Power Supply VD - Digital Supply, PIN 4(L), 42(Q). +5V or +3.3V digital supply. VA - Analog +5V Supply, PIN 24(L), 18(Q). +5V analog supply. DGND - Digital Ground, PIN 5(L), 43(Q). Digital ground. Must be connected to AGND with zero impedance.
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AGND - Analog Ground, PIN 23(L), 17(Q). Analog ground. Must be connected to DGND with zero impedance. Analog Inputs RIN1 - Right Input #1, PIN 25(L), 19(Q). Right analog input #1. Full scale input, with no gain, is 1Vrms, centered at REFBUF. RIN2 - Right Input #2, PIN 26(L), 20(Q). Right analog input #2. Full scale input, with no gain, is 1Vrms, centered at REFBUF. LIN1 - Left Input #1, PIN 27(L), 21(Q). Left analog input #1. Full scale input, with no gain, is 1Vrms, centered at REFBUF. LIN2 - Left Input #2, PIN 28(L), 22(Q). Left analog input #2. Full scale input, with no gain, is 1Vrms, centered at REFBUF. Analog Outputs ROUT - Right Channel Output, PIN 15(L), 9(Q). Right channel analog output. Maximum signal is 1 Vrms centered at REFBUF. LOUT - Left Channel Output, PIN 16(L), 10(Q). Left channel analog output. Maximum signal is 1 Vrms centered at REFBUF. REFBYP - Analog Reference Decoupling, PIN 21(L), 15(Q). A 10 F and 0.1 F capacitor must be attached between REFBYP and REFGND. REFGND - Analog Reference Ground Connection, PIN 22(L), 16(Q). Connect to AGND. REFBUF - Buffered Reference Out, PIN 20(L), 14(Q). A nominal +2.1V output for setting the bias level for external analog circuits. Serial Digital Audio Interface Signals SDIN - Serial Port Data In, PIN 42(L), 36(Q). Digital audio data to the DACs and level control information is received by the CS4218 via SDIN. SDOUT - Serial Port Data Out, PIN 43(L), 37(Q). Digital audio data from the ADCs and status information is output from the CS4218 via SDOUT. SCLK - Serial Port Bit Clock, PIN 44(L), 38(Q). SCLK controls the digital audio data on SDOUT and latches the data on SDIN. SCLK must be synchronous to the master clock.
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CS4218
SSYNC - Serial Port Sync Signal, PIN 1(L), 39(Q). Indicates the start of a digital audio frame. SSYNC must be synchronous to the master clock. SMODE1 - Serial Mode Select, PIN 29(L), 23(Q). One of three pins that select the serial mode and function of the multifunction pins. SMODE2 - Serial Mode Select, PIN 32(L), 26(Q). One of three pins that select the serial mode and function of the multifunction pins. SMODE3 - Serial Mode Select, PIN 41(L), 35(Q). One of three pins that select the serial mode and function of the multifunction pins. Multifunction Digital Pins MF1:F1 - Format bit 1 in SM3 and SM5, PIN 40(L), 34(Q). In SM3-M, SM3-MM, and SM5, this pin is a format bit and is used as one of three sample frequency select pins, or as one of two bits-per-frame select pins when in SM3-S or SM3-MS. MF1:CDOUT - Control Data Output in SM4, PIN 40(L), 34(Q). In serial mode 4 this pin is the data output for the control port which contains status information. MF2:F2 - Format bit 2 in SM3 and SM5, PIN 39(L), 33(Q). In SM3-M, SM3-MM, and SM5, this pin is a format bit and is used as one of three sample frequency select pins , or as one of two bits-per-frame select pins when in SM3-S or SM3-MS. MF2:CDIN - Control Data Input in SM4, PIN 39(L), 33(Q). In SM4 this pin is the control port data input which contains data such as gain and attenuation settings as well as input select, mute, and digital output bits. MF3:F3 - Format bit 3 in SM3 and SM5, PIN 35(L), 29(Q). In SM3-M, SM3-MM, and SM5, this pin is a format bit and is used as one of three sample frequency select pins. In SM3-S and SM3-MS, the pin reverts to being a general purpose input. MF3:CCLK - Control Data Clock in SM4, PIN 35(L), 29(Q). In SM4 this pin is the control port serial bit clock which latches data from CDIN on the falling edge, and outputs data onto CDOUT on the rising edge. MF4:MA - Master sub-mode in SM3, PIN 36(L), 30(Q). In SM3, this pin selects either master or slave sub-modes. When MF4:MA = 1, the codec is in master sub-modes and outputs SSYNC and SCLK. When MF4:MA = 0, the codec is in slave sub-modes and receives SSYNC and SCLK from an external source that must be frequency locked to CLKIN. MF4 - SM5, PIN 36(L), 30(Q). In SM5, this pin is not used and should be tied to VD.
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MF4:CCS - Control Data Chip Select in SM4, PIN 36(L), 30(Q). In SM4 this pin is the control port chip select signal. When low, the control port data is clocked in CDIN and status data is output on CDOUT. When CCS goes high, control data is latched internally. This data remains active until new data is clocked in. The control port may also be asynchronous to the audio data port. MF5:DO2 - Parallel Digital Bit Output #2 in SM3 and SM5, PIN 38(L), 32(Q). In SM3 and SM5, this pin reflects the value of the DO2 bit in the sub-frame. MF5:INT - Interrupt in SM4, PIN 38(L), 32(Q). In SM4 this pin is an active low interrupt signal that is maskable using the MSK bit in the control port serial data stream. INT is an open-collector output and requires and external pull-up resistor. Assuming the mask bit is not set, and interrupt is triggered by a change in ADV or DI1, or a rising edge on LCL or RCL, or when exiting an SCLK out of range condition (Error = 3) MF6:DI2 - Parallel Digital Bit Input #2 in SM3 and SM5, PIN 34(L), 28(Q). In SM3 and SM5, this pin value is reflected in the DI2 bit of the sub-frame. MF6:F1 - Format Bit 1 in SM4, PIN 34(L), 28(Q). In SM4 this pin is a format bit and is used as one of three sample frequency select pins when in master mode. In slave mode, MF6:F1 is used to determine the number of sub-frames within a frame. MF7:SFS1 - Sub-Frame Select 1 in SM3/SM4-SL, PIN 31(L), 25(Q). In SM3, MF7:SFS1 helps select the sub-frame that this particular CS4218 is allocated. In slave sub-mode of SM4, this pin is one of two pins used as a sub-frame select when MF6:F1 = 1 (128-bit frames). When MF6:F1 = 0, this pin is used to select the frame sizes of 32 or 64 bits. MF7 - SM5, PIN 31(L), 25(Q). In SM5, this pin is not used and should be tied to DGND. MF7:F2 - Format Bit 2 in SM4-MA, PIN 31(L), 25(Q). In master sub-mode of SM4, this pin is used as one of three sample frequency select pins. MF8:SFS2 - Sub-Frame Select 2 in SM3/SM4-SL, PIN 30(L), 24(Q). In SM3 and slave sub-mode of SM4, MF8:SFS2 helps select the sub-frame that this particular CS4218 is allocated. MF8 - SM5, PIN 30(L), 24(Q). In SM5, this pin is not used and should be tied to DGND. MF8:F3 - Format Bit 3 in SM4-MA, PIN 30(L), 24(Q). In master sub-mode of SM4, this pin is a format bit and is one of three sample frequency select pins.
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CS4218
Miscellaneous RESET - Reset Input, PIN 2.(L), 40(Q). Resets the CS4218 to a known state, and must be initiated after power-up or power-down mode. Releasing RESET causes the CS4218 to initiate a calibration sequence. The CS4218 automatically initiates a calibration sequence after a sample rate change in master and slave modes. CLKIN - Master Clock, PIN 3(L), 41(Q). CLKIN is the master clock that operates the internal logic. CLKIN is 256xFsmax, where Fsmax is the highest sample frequency needed, for SM3 Master and Slave, and for SM4 Master and Slave. CLKIN is 16xFsmax in SM3 Multiplier sub-modes. Different sample frequencies are obtained by either changing the ratio of SCLK to CLKIN in slave modes, or changing the format pin values (F2-F0) in master modes. PDN - Power Down, PIN 13(L), 7(Q). This pin, when low, causes the CS4218 to go into a power down state. RESET should be held low for 50 ms when exiting the power down state to allow time for the voltage reference to settle. DI1 - Parallel Digital Bit Input #1, PIN 33(L), 27(Q). This pin value is reflected in the DI1 bit in the sub-frame. DO1 - Parallel Digital Bit Output #1, PIN 37(L), 31(Q). This pin reflects the value of the DO1 bit in the sub-frame FILT - PLL Filter, PIN 6(L), 44(Q). This pin should have the 0.47 F PLL loop filter capicator connected when using SM3 Multiplier sub-modes. When using SM3-M, SM3-S, SM4, or SM5 modes, this pin should be left floating. This pin has an internal pull-down making the CS4218 pin compatible with the CS4216 operating in serial modes SM3-M, SM3-S, and SM4. NC - No Connection, PINS 7, 8, 9, 10, 11, 12, 14, 17, 18, 19(L) PINS 1, 2, 3, 4, 5, 6, 8, 11, 12, 13(Q). These pins should be left floating with no trace attached to allow backwards compatibility with future revisions. They should not be used as a convenient path for signal traces.
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PACKAGE DIMENSIONS
44 PIN PLCC
NO. OF A TERMINALS MIN MAX 17.40 17.65 (0.685) (0.695)
B MIN MAX MIN
C MAX
44
16.51 16.66 (0.650) (0.656)
14.98 16.00 (0.590) (0.630) B
A
1.27(0.050) x45deg.NOM
4.62 (0.182) 4.11 (0.162) 1.14 (0.045) 0.63 (0.025) 2.41 (0.095) MIN 0.25 (0.010) R MAX
1.14 (0.045) x 45deg. NOM B A
C
0.46 ( 0.018 ) 0.33 ( 0.013 ) 3 NOM
1.35 (0.053) 1.19 (0.047)
3 NOM
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
44 PIN QUAD FLATPACK
A B
DIM A B C D E F G H I J K L M N
1
B
A
44 Pin TQFP 1.4 mm Package Thickness MILLIMETERS INCHES MIN MAX MIN MAX 11.75 0.482 0.463 12.25 0.390 0.398 9.90 10.10 0o 7o 0o 7o 0.80 BSC 0.031 BSC 0.35 BSC 0.014 BSC 12 o 12 o 0.021 0.029 0.54 0.74 0.021 0.029 0.54 0.74 0.053 0.059 1.35 1.50 0.002 0.05 0.063 1.60 0.007 0.17 10 o 2o 2o 10 o 0.026 0.014 0.35 0.65
F G HI J K L
M
C
D
E
N
0.102 MAX Lead Coplanarity
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CS4218
PARAMETER DEFINITIONS Resolution The number of bits in the input words to the DACs, and in the output words from the ADCs. Differential Nonlinearity The worst case deviation from the ideal codewidth. Units in LSB. Total Dynamic Range TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. It is measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e. attenuation bits for the DACs at full attenuation). Units in dB. Instantaneous Dynamic Range IDR is the ratio of a full-scale rms signal to the rms noise available at any instant in time, without changing the input gain or output attenuation settings. It is measured using S/(N+D) with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal. Use of a small input signal reduces the harmonic distortion components to insignificance when compared to the noise. Units in dB. Total Harmonic Distortion THD is the ratio of the rms value of a signal's first five harmonic components to the rms value of the signals fundamental component. THD is calculated using an input signal which is 3dB below typical full-scale, and is referenced to typical full-scale. Interchannel Isolation The amount of 1 kHz signal present on the output of the grounded input channel, with 1 kHz 0 dB signal present on the other channel. Units in dB. Interchannel Gain Mismatch For the ADCs, the difference in input voltage that generates the full scale code for each channel. For the DACs, the difference in output voltages for each channel with a full scale digital input. Units in dB. Frequency Response Worst case variation in output signal level versus frequency over the passband. Tested over the frequency band of 10 Hz to 20 kHz, with the sample frequency of 48 kHz. Units in dB. Step Size Typical delta between two adjacent gain or attenuation values. Units in dB. Absolute Gain/Attenuation Step Error The deviation of a gain or attenuation step from a straight line passing through the no-gain/attenuation value and the full-gain/attenuation value (i.e. end points). Units in dB. Offset Error For the ADCs, the deviation of the output code from the mid-scale with the selected input at REFBUF. For the DACs, the deviation of the output from REFBUF with mid-scale input code. Units in LSB's for the ADCs and volts for the DACs.
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Out of Band Energy The ratio of the rms sum of the energy from 0.46xFs to 2.1xFs compared to the rms full-scale signal value. Tested with 48 kHz Fs giving a out-of-band energy range of 22 kHz to 100 kHz.
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CS4218
Appendix A: CS4218 Compatibility with CS4216 IMPORTANT !! If you are upgrading your design from the CS4216 to the CS4218, please make sure to read this entire appendix. The CS4218 is pin compatible with the CS4216. This appendix provides a summary of differences between the two codecs. Pin Compatibility The CS4218 is 100% pin compatible with the CS4216 when used in Serial Modes 3 and 4. The differences are noted in the following paragraphs and tables. The CS4218 integrates the 600-ohm series resistors for the LOUT and ROUT analog outputs on the IC itself. For the CS4216, these resistors are not on-chip, and need to be provided externally. The CS4218 pin named SMODE3 does not incorporate an on-chip pull-down resistor, as is provided on the CS4216 Rev B and later. This pin must be tied high or low, or driven by control logic to the desired state (depends on the serial mode used). If this pin is left floating, the codec will not work correctly. The CS4218 adds the pin named FILT. On the CS4216, this pin is a no connect. The FILT pin is only used when employing the SM3 Multiplier sub-mode. When using this sub-mode, a 0.47uF capacitor must be connected from the FILT pin to AGND. When not using the Multiplier sub-mode, this pin may remain unconnected. Serial Modes The CS4218 supports Serial Modes 3 and 4 of the CS4216. In addition, the CS4218 provides the SM3 Multiplier sub-mode and Serial Mode 5, which are not provided on the CS4216. The CS4218 does not support Serial Modes 1 and 2 of the CS4216. Decimation and Interpolator Filter Responses The CS4218 and CS4216 use different digital filters for the ADC decimators and DAC interpolators. Tables A1 and A2 provide a comparison between each codec's filter responses.
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Parameter Passband Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay Units Hz dB Hz Hz dB sec CS4218 0-0.4Fs 0.1 0.4-0.6Fs 0.6Fs 74dB 8/Fs TABLE A1: Decimation Filter Comparison CS4218 0-0.4Fs 0.1 0.4-0.6Fs 0.6Fs 74dB 8/Fs TABLE A2: Interpolation Filter comparison CS4216 0-0.45Fs 0.2 0.45-0.55 0.55Fs 80dB 16/Fs
Parameter Passband Passband Ripple Transition Band Stop Band Stop Band Rejection Group Delay
Units Hz dB Hz Hz dB sec
CS4216 0-0.45Fs 0.1 0.45-0.55 Fs 0.55Fs 74dB 16/Fs
Digital Power Supplies and Input Logic Levels The CS4218 and CS4216 both require that the analog power supply be 5V +/- 0.25V. The CS4218 digital power supply can operate from 5V +/- 0.25V and 3.3V +/- 0.3V. When operated from a 5V supply, the CS4218 is TTL and CMOS compatible inputs & outputs. When operated from a 3.3V power supply, the CS4218 is LVTTL and LVCMOS compatible. In comparison, the CS4216 operates from a 5V +/- 0.25V power supply. It provides only CMOS logic level inputs. The CS4216 requires level-translation logic (using the 74HCT family) when interfacing it's inputs with TTL logic.
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CS4218
Appendix B: Applications of SM4 Figure B1 illustrates one method of using Serial Mode 4 wherein a DSP controls the audio serial port and a microcontroller controls the control port. Each controller is run independently and the micro updates the control information only when needed, or when an interrupt from the CS4218 occurs. Figure B2 illustrates the minimum interface to the CS4218. In this application, the DSP sends and receives stereo DAC and ADC information. The CS4218 is configured for 32 bits per frame, Master sub-mode. The control data resets to all zeros, which configures the CS4218 as a simple stereo codec: no gain, no attenuation, line inputs #1, and DAC outputs not muted. Figure B3 illustrates how to use all the CS4218 features with a low cost DSP that cannot support the interrupt rate of SM3. Using SM4 (32 bits per frame, Master sub-mode) reduces the DSP interrupts in half since the control data is split from the audio data. This circuit is comprised of three independent sections which may individually be eliminated if not needed.
SDOUT SDIN SSYNC SCLK
43
SDOUT
42
43
SDIN
1 44
42
1 44
DSP
DSP
SSYNC SCLK CS4218
CS4218 SM4 VD+ MicroController
SM4 32 BPF MF3:CCLK 35 36 38 40 39 2 34 31 30
VD+
MF1:CDOUT MF2:CDIN MF4:CCS MF3:CCLK
MF5:INT RESET MF6:F1
40 39 36 35 38 2 34 31 30 General Purpose Port Pins IRQ Serial Port
MF4:CCS
MF5:INT MF1:CDOUT MF2:CDIN RESET MF6:F1
Hard Wired or
DIP Switch selectable
MF7:F2
MF8:F3
MF7:F2
MF8:F3
Figure B1. SM4 - Microcontroller Interface 40
Figure B2. SM4 - Minimum DSP Interface DS135F1
CS4218
43 SDOUT 42 SDIN 1 SSYNC 44 SCLK DSP
VD+ 35 MF3:CCLK 36
MF4:CCS
38
MF5:INT 39 MF2:CDIN HC597 DOUT LOAD HC597 HC597 DIN
CS4218
SM4 32 BPF 40 MF1:CDOUT A B LCLK C D AIN E F HC595 G H OE SCLK 0 ADV DI1 RCL LCL ERR0 ERR1 1 CS^STATUS 2 RESET 34 MF6:F1 31 MF7:F2 30 MF8:F3 HC574 CS^FS
CS^CONTROL
24+ bit DSP Data Bus
Figure B3. SM4 - Enhanced DSP Interface DS135F1 41
CS4218
To load control data into the codec, three HC597's are utilized. These are the latches that store the DSP-sent control data, and shift registers that shift the data into the codec. The codec uses an inverted SSYNC signal to copy the latches to the shift registers every frame. In this diagram the DSP is assumed to have a data bus bandwidth of at least 24 bits. If the DSP has less than 24-bits, the three HC597s must be split into two addresses. Since the HC597 internal latches are copied to the shift registers, the latches continually hold the DSP-sent data; therefore, the DSP only needs to write data to the latches when a change is desired. The second section is comprised of an HC595 shift register and latch that is clocked by an inverted SCLK. The data shifted into the HC595 is transferred to the HC595's latch by the SSYNC signal. This HC595 captures the 8 bits prior to the SSYNC signal (which is also MF4:CCS) going high. As shown in Figure 12, and assuming the MF4:CCS (SSYNC) signal rises at bit 32, the 8-bits prior to MF4:CCS rising are a copy of all the important status bits. This allows one shift register to capture all the important information. The interrupt pin cannot reliably be used in this configuration since the interrupt pin is cleared by reading the control port which occurs asynchronously (every audio frame) with respect to the interrupt occurrence. The third section is only needed if sample frequencies need to be changed. This section is comprised of an HC574 octal latch that can be replaced by general purpose port pins if available. This section controls the sample frequency selection bits: MF6:F1, MF7:F2, MF8:F3 and the RESET pin. A change in sample rate automatically initiates a calibration cycle.
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Appendix C: Setting CLKIN/SCLK Ratio for Desired Sample Rate In Slave sub-modes, the CS4218 detects the ratio between the CLKIN and SCLK rates and sets the internal sample rate accordingly. The following formula can be used to determine the ratio of CLKIN to SCLK for any desired sample rate for both Serial Modes 3 and 4, Slave sub-modes. CLKIN (256 x Fsmax) = SCLK (BPF x Fs) where: CLKIN = Master clock input In SM3 Multiplier Slave sub-mode, CLKIN is replaced by 16* CLKIN. SCLK = Serial port bit clock. Fsmax = Maximum system sample rate. Fs = Desired sample rate. BPF = The number of bits per frame (256, 128, 64 or 32)
Example 1: SM3-S, Fsmax = 48 kHz, Fs = 8 kHz, BPF = 64 12.288 MHz CLKIN (256 x 48000) = = = 24 512 kHz SCLK (64 x 8000) Example 2: SM4-S, Fsmax = 8 kHz, Fs = 8 kHz, BPF = 32 CLKIN (256 x 8000) 2.048 MHz = = =8 SCLK 256 kHz (32 x 8000)
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Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation

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